1. Field of the Invention
The present invention relates to multiplying complex numbers with a processor.
2. Related Art
In older designs for signal processing systems (such as a Digital Subscriber Line (DSL) modem), which are in general more hardware oriented, functions on complex values, such as the signal equalization process and performing a Fast Fourier Transform (FFT), may be performed by fixed-function logic circuits. However, such system designs are usually difficult to adapt for varying application requirements. In order to increase flexibility in modem development and application, it has become more common to use software to perform the various functions in a signal processing device. As performance levels (such as data rates) required of such devices increase, the requirements of the software efficiently to perform individual processing tasks (such as equalization or FFT) likewise increases.
Performing complex multiplication in software is somewhat complicated to implement. Using conventional instructions (e.g., scalar multiply, add, subtract) it may take several cycles to perform a single complex multiplication. In some circumstances (e.g., in a DSL modem, especially in the case of a multi-channel implementation using a single processor to handle multiple channels), it may be necessary to perform millions of complex multiplications every second, as part of the Fast Fourier Transform (FFT) and/or equalization processes.
The complex multiplication process can therefore represent a significant proportion of the total computational cost for a signal processing system, especially in the case of a system where one processor handles the operations for multiple independent processing channels (e.g., in a multi-line DSL modem in a central office). With increasing workloads—in respect of the increasing complexity of the signal processing protocols (e.g., the number of frequencies for which equalization may be needed, in each channel)—it becomes necessary to improve the efficiency of complex multiplication in such systems.
A further problem concerns details of the equalization process as applied to data values representing two-dimensional data, such as complex frequency amplitudes in a signal processing system (e.g., a receiver for Discrete MultiTone (DMT) transmissions).
In some circumstances, the magnitudes of the input data values (and hence also the equalization factors whose magnitudes will be in inverse proportion to those of the data values) can range widely from one input position (e.g., frequency) to another. In these cases, using a complex multiplication step in which the scaling of the operands is the same for all input positions can be sub-optimal. A fixed scaling has to be chosen carefully. On the one hand, it must handle the case of those input values to be equalized which have the smallest magnitudes (and hence the largest equalization factor magnitudes) without the equalization factor magnitudes overflowing the available range. On the other hand, it must also work with the largest input data values (using the smallest equalization factors) without losing precision as a result of coarse quantization of the equalization factors because of their small magnitudes. This latter aspect is important because, in cases such as DMT, it is often those data values of largest original magnitude that carry the most information and in which the decoding process is most sensitive to errors in the equalized values arising from quantization of the equalization factors.
For these and other reasons, more efficient methods and systems for complex multiply-accumulate operations are needed.